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r03ds0064ej0100 rev.1.00 page 1 of 29 aug 03, 2012 preliminary datasheet rna50c27a cmos system-reset ic description this ic facilitates complicated power-on and power-monitoring resets of micr ocomputers that require the 3.3-v and 1.8-v dual power supplies. it also facilitates change of delay time of reset signal by externally setting resistance and capacity for delay time. by employing complementary open-drain output, desired output such as open-drain output and cmos output can be obtained. functions ? 3.3-v detection voltage : 2.7 v ? accuracy of 3.3-v detection voltage : ? 1.0% ? hysteresis of 3.3-v detection voltage : 5% typ. ? 1.8-v detection voltage : 0.9 v typ. ? open-drain/cmos output ? 1.8-v pmos drive output ? package : 8-pin ssop-8/mmpak-8 ? operating temperature : ?40 to +85c ordering information part name package type package code package abbreviation taping abbreviation (quantity) surface treatment rna50c27ausel-e ssop-8 pvsp0008ka-a us el (3,000 pcs / reel) e (sn-bi) rna50c27ammel-e mmpack-8 plsp0008jc-a mm el (3,000 pcs / reel) e (sn-bi) block diagram ? + 1 8 mr v dd 33 2 resp 3 res n 6v dd 18 vref delay 7 crext 4 gnd 5 swg r03ds0064ej0100 rev.1.00 aug 03, 2012
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 2 of 29 aug 03, 2012 pin arrangement 18 4 3 2 mr swg (top view) v dd 18 crext 6 7 5 v dd 33 resn resp gnd pin description pin no. pin name function 1 v dd 33 input power supply pin for 3.3 v voltage. recommended operating range is v th 33 to 3.6 v. set input voltage to 0.033 v/ ? s or less when starting up. if input voltage terminal v dd 33 was momentary (v dd 33 pin input voltage is lower than detection voltage state period of short), for discharge of external capacitance becomes insufficient, delay time will be very short. please check if there is any problem as a system. 2 resp pull-down when reset signal output pin. by connecting to resn pin, cmos output can be used. 3 resn pull-up when reset signal output pin. by connecting to resp pin, cmos output can be used. 4 gnd gnd pin 5 swg to be installed between 1.8 v power supply and 1.8 v voltage input of microcomputer, gate of pmos is external control signal. it has been designed with load capacity of 2200 pf typ., will change size of rise time/fall time of swg capacity. 6 v dd 18 input power supply pin for 1.8 v voltage. recommended operating range is 1.65 v to v dd 33. when terminal voltage is below 0.9 v typ, and outputs high-level signal swg. 7 crext terminal is for determining rext resistance and cext capacitance of reset signal delay time. resistance is recommended for more than 3.3 k ? . delay time is given by tdly = cext ? rext [s] does not output reset signal when this pin is not high-level. connect external resistor for v dd 33 necessarily. 8 mr this terminal outputs a reset signal manually. has been pull-up internally 2 m ? . if behavior is unstable, behavior is stabilized by connecting 220 pf to this pin to gnd. in addition, or when connected to potential, such as v dd 33 to force this pin to external, pulse width input to the mr be shorter than discharge time of crext is, please note for delay normal can not be obtained.
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 3 of 29 aug 03, 2012 absolute maximum ratings (ta = 25c) item symbol terminal ratings unit remarks v dd 33 v dd 33 4.6 supply voltage v dd 18 v dd 18 4.6 v input voltage v i mr , crext ?0.3 to v dd 33 v resp, resn ?0.3 to v dd 33 output voltage v o swg ?0.3 to v dd 18 v input current i i mr , crext 20 ma output current i o resp, resn , swg 20 ma supply current i dd v dd 33, v dd 18 25 ma 160 ssop-8 power dissipation p t ? 145 mw mmpak-8 storage temperature tstg ? ?55 to +125 c recommended operating conditions (ta = 25c) item symbol terminal min typ max unit remarks v dd 33 v dd 33 v th 33 ? 3.6 supply voltage v dd 18 v dd 18 1.65 ? v dd 33 v input voltage v i mr , crext 0 ? v dd 33 v resp 0 ? v dd 33 resn 0 ? v dd 33 output voltage v o swg 0 ? v dd 18 v external resistor rext crext 3.3 ? ? k ? v dd 33 = 3.3v external capacitor cext crext ? nolimit ? f mr pin capacitor c mr mr ? 220 ? pf drivable capacitor c l swg ? 2200 ? pf swg output operating temperature ta ? ?40 ? 85 c
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 4 of 29 aug 03, 2012 electrical characteristics dc characteristics (v dd 33 = 3.3v, v dd 18 = 1.8v, ta = 25c, rext = 10k ? ) item symbol min typ m ax unit test conditions i dd 33 0.6 2.0 8.0 quiescent supply current i dd 18 0.3 1.0 3.0 ? a v th 33 2.673 2.700 2.727 v th 18h 1.2 ? ? detection voltage v th 18l ? ? 0.6 v detection voltage temperature dependency v th 33 v th 33 ? ta ? ( ?100) ? ppm/c detection voltage hysteresis v hys v th 33? 1.03 v th 33? 1.05 v th 33?1.08 v low-level input voltage v il ? ? 0.495 v high-level input voltage v ih 2.805 ? ? v mr internal pull-up resistance rmr ? (2.0) ? m ? low-level output current i ol 5 15 20 v o = 0.5v cmos high-level output current i oh 5 10 13 ma v o = 2.8v output leakage current i oleak ? (0.1) ? ? a v o = 0.5v resp high-level output current i oh 5 10 13 ma v o = 2.8v low-level output current i ol 5 15 20 ma v o = 0.5v resn output leakage current i oleak ? (0.1) ? ? a v o = 2.8v low-level output current i ol 0.2 0.35 0.6 v o = 0.5v high-level output current i oh 1.0 3.0 6.0 ma v o = 1.3v low-level output voltage v ol ? ? 0.1 swg high-level output voltage v oh 1.7 ? ? v swg = open note: when the voltage within v il < v in < v ih is applied to mr and v dd 18 input by dc, oscillation may occur. when resp output and resn short out and cmos output is used. ac characteristics (v dd 33 = 3.3v, v dd 18 = 1.8v, ta = 25c, rext = 10k ? , r l = 100k ? , c l = 15pf) item symbol min typ m ax unit test conditions tplh ? ? (500) * 1 propagation delay time tphl ? ? (100) * 1 ? s tr ? ? (100) * 1 cmos response time tf ? ? (100) * 1 ns tplh ? ? 500 * 2 propagation delay time tphl ? ? (100) * 3 ? s tr ? ? (100) * 3 ns resp response time tf ? ? (100) * 3 ? s tplh ? ? 500 * 2 propagation delay time tphl ? ? (100) * 3 ? s tr ? ? (100) * 3 ? s resn response time tf ? ? (100) * 3 ns tphl ? ? 500 * 2 propagation delay time tplh ? ? 100 * 2 ? s c l = 2200pf tf ? (10) * 3 ? swg response time tr ? (5) * 3 ? ? s c l = 2200pf delay time tdly ? (93) * 2 ? ms cext = 0.1 ? f, rext = 1m ? notes: ( ) is a design reference value. * 1 estimated from measured value of resp, resn (will vary considerably depending on conditions). * 2 edge is triggered 0 v ?3.3 v, 3.3 v ? 0 v when change of maximum delay path v dd 33. * 3 signal to trigger mr .
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 5 of 29 aug 03, 2012 timing chart vop_min v hys v ih t dly t dly t dly t dly t dly t dly v th 33 v th 18l v th 18h v il v dd 33 v dd 18 mr *1 res swg note: mr has been pulled up to v cc by the internal resistance. timing diagram is in phase with signal of v dd 33.
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 6 of 29 aug 03, 2012 table of graphs dc characteristics item symbol vs. v dd 33 vs. v dd 18 vs. ta other test circuit i dd 33 fig. 1-1 ? fig. 3-1 ? 1 quiescent supply current i dd 18 ? fig. 2-1 fig. 3-2 ? 1 v th 33 ? ? fig. 3-3 ? 2 v th 18h ? ? fig. 3-5 ? 3 detection voltage v th 18l ? ? fig. 3-5 ? 3 detection voltage temperature dependency ? ? ? ? 2 detection voltage hysteresis v hys ? ? fig. 3-4 ? 2 v il fig. 1-2, 3 ? fig. 3-6 ? 4 input voltage v ih fig. 1-2, 3 ? fig. 3-6 ? 4 mr internal pulled-up resistor rmr ? ? fig. 3-7 ? 5 i oleak fig. 1-4 ? fig. 3-8 ? 8 resp output current i oh fig. 1-5 ? fig. 3-9 ? 7 i ol fig. 1-6 ? fig. 3-10 ? 6 resn output current i oleak fig. 1-7 ? fig. 3-11 ? 9 i ol ? fig. 2-2 fig. 3-12 ? 13 swg output current i oh ? fig. 2-3 fig. 3-13 ? 11 ac characteristics item symbol vs. v dd 33 vs. v dd 18 vs. ta other test circuit tplh fig. 1-8 ? fig. 3-14 ? 14 propagation delay time tphl fig. 1-9 ? fig. 3-15 ? 17 tr fig. 1-10 ? fig. 3-16 ? 20 resp response time tf fig. 1-11 ? fig. 3-17 ? 23 tplh fig. 1-12 ? fig. 3-18 ? 15 propagation delay time tphl fig. 1-13 ? fig. 3-19 ? 18 tr fig. 1-14 ? fig. 3-20 ? 21 resn response time tf fig. 1-15 ? fig. 3-21 ? 24 tphl fig. 1-16 ? fig. 3-22 ? 16 propagation delay time tplh fig. 1-17 ? fig. 3-23 ? 19 tf fig. 1-18 ? fig. 3-24 ? 22 swg response time tr fig. 1-19 ? fig. 3-25 ? 25 delay time tdly fig. 1-20 fi g. 2-4 fig. 3-26 fig. 4-1 26
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 7 of 29 aug 03, 2012 test circuits swg mr v dd 18 gnd resn resp crext v dd 33 1. quiescent supply curren, i dd 33, i dd 18 v dd 33 = 3.3 v v dd 18 = 1.8 v i dd 33 i dd 18 a a rext = 10 k 2. detection voltage, v th 33 v1 v1 v1 v hys swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 v dd 33 v th 33 v dd 33 v dd 18 = 1.8 v v rext = 10 k 3. detection voltage, v th 18h, v th 18l v1 release voltage v1 v1 v dd 18 detection voltage swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 v th 18h v th 18l v dd 18 v v dd 33 = 3.3 v rext = 10 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 8 of 29 aug 03, 2012 vmr vmr release voltage detection voltage swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v v1 v dd 33 v dd 33 v vmr v1 v1 v ih v il 4. mr pin input voltage low-level / high-level, v il /v ih vmr rmr = [ ] (v 2 ? v 1 ) (i 2 ? i 1 ) v1 i2 v2 i1 swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v v vmr a imr imr 5. mr pin internal pulled-up resistor, rmr swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v i ol rext = 10 k v dd 18 = 1.8 v v o = 0.5 v a 6. cmos(resn) output current low-level, i ol
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 9 of 29 aug 03, 2012 swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v v o = 2.8 v a i oh 7. cmos(resp) output current high-level, i oh 8. resp pin output leakage current, i oleak swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v v o = 0.5 v a i oleak 9. resn pin output leakage current, i oleak swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v o = 2.8 v a v dd 18 = 1.8 v i oleak
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 10 of 29 aug 03, 2012 10. swg output voltage high-level, v oh swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v v dd 33 = 3.3 v rext = 10 k v 11. swg pin output current high-level, i oh swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v v dd 33 = 3.3 v rext = 10 k a v o = 1.3 v i oh swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v v 12. swg output voltage low-level, v ol swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v a v o = 0.5 v i ol 13. swg pin output current low-level, i ol
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 11 of 29 aug 03, 2012 14. propagation delay time resp, tplh t swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 = 3.3 vpp v o r l rext = 10 k v dd 18 = 1.8 v v dd 33 tplh tplh 3.3 v 3.3 v 0 v 0 v 1.65 v v o v o v v 15. propagation delay time resn, tplh t swg mr v dd 18 gnd resn resp crext v dd 33 r l v dd 33 3.3 v 3.3 v 0 v 0 v 1.65 v v o v dd 18 = 1.8 v v v dd 33 = 3.3 vpp rext = 10 k v t v o swg mr v dd 18 gnd resn resp crext v dd 33 v dd 33 tphl 1.8 v 3.3 v 0 v 1.8 v v hys v hys v hys 0.9 v v o v dd 18 = 1.8 v c l = 2200 pf v v dd 33 = 3.3 vpp rext = 10 k v 16. propagation delay time swg, tphl r l = 100 k r l = 100 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 12 of 29 aug 03, 2012 17. propagation delay time resp, tphl v o r l v r l = 100 k swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v 18. propagation delay time resn, tphl 19. propagation delay time swg, tplh t 3.3 v 3.3 v 3.3 v 3.3 v 1.65 v 1.65 v v o vmr swg mr v dd 18 gnd resn resp crext v dd 33 r l = 100 k v dd 18 = 1.8 v vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v v o r l v t 3.3 v 3.3 v 3.3 v 3.3 v 1.65 v 1.65 v v o vmr tphl tphl swg mr v dd 18 gnd resn resp crext v dd 33 v o v dd 18 = 1.8 v c l = 2200 pf v vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v t 3.3 v 1.65 v vmr 0 v tplh 1.8 v 3.3 v 0.9 v v o
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 13 of 29 aug 03, 2012 20. rising response time resp, tr tr v o r l v r l = 100 k swg mr v dd 18 gnd resn resp crext v dd 33 vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v t 3.3 v 0 v v o 2.97 v 0.33 v 21. rising response time resn, tr tf v dd 33 = 3.3 v rext = 10 k swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v c l = 2200 pf v vmr = 3.3 vpp t 1.8 v 0 v v o v o 1.62 v 0.18 v 22. falling response time swg, tf tr vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v o r l v r l = 100 k swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v t 3.3 v 0 v v o 0.33 v 2.97 v
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 14 of 29 aug 03, 2012 23. falling response time resp, tf v o r l v r l = 100 k swg mr v dd 18 gnd resn resp crext v dd 33 vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v dd 18 = 1.8 v t t 3.3 v 3.3 v 0 v 0 v tf 0.33 v 2.97 v 0.33 v 2.97 v tf 24. falling response time resn, tf vmr = 3.3 vpp v dd 33 = 3.3 v rext = 10 k v o r l v r l = 100 k swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v v dd 33 = 3.3 v rext = 10 k swg mr v dd 18 gnd resn resp crext v dd 33 v dd 18 = 1.8 v c l = 2200 pf v vmr = 3.3 vpp v o 25. falling response time swg, tr 0.18 v tr t 1.8 v 0 v v o v o v o 1.62 v
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 15 of 29 aug 03, 2012 t swg mr v dd 18 gnd resn resp crext v dd 33 26. delay time, tdly v dd 33 tdly 3.3 v 3.3 v 0 v 0 v 1.65 v v o v dd 18 = 1.8 v cext = 0.1 f v o v v dd 33 = 3.3 vpp rext = 1 m v v hys
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 16 of 29 aug 03, 2012 main characteristics 1.0e?07 234 supply voltage, v dd 33 (v) figure 1-1. supply current vs. supply voltage figure 1-2. manual reset threshold voltage of reset output vs. supply voltage 5 234 supply voltage, v dd 33 (v) 5 5 0 1 2 3 4 1.0e?06 1.0e?05 supply current, i dd 33 (a) manual reset threshold voltage, vrm (v) 1.0e?04 1.0e?03 ?1.0e?07 024 13 output voltage, v ol (v) figure 1-4. resp output leakage current vs. output voltage 5 ?5.0e?08 0.0e+00 output leakage current, io leak (a) 5.0e?08 1.0e?07 manual reset threshold voltage, vrm (v) figure 1-3. manual reset of output threshold voltage swg vs. supply voltage 234 supply voltage, v dd 33 (v) 5 5 0 1 2 3 4 ?0.10 ?0.08 024 13 differential output voltage from v dd 33, v oh (v) figure 1-5. resp output current vs. output voltage 5 ?0.06 ?0.04 output current, i oh (a) ?0.02 0.00 ta = 25c, v_mr = 0 v ta = 25c, v_mr = v dd 33 v v dd 33 = 2.4 v v ih v il v dd 33 = 3.3 v v dd 33 = 4.6 v v dd 33 = 2.4 v, v dd 33 = 3.3 v, v dd 33 = 4.6 v v ih , v il
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 17 of 29 aug 03, 2012 figure 1-8. resp output rising propagation delay time vs. supply voltage figure 1-10. resp output rising response time vs. supply voltage figure 1-11. resp output falling response time vs. supply voltage 234 supply voltage, v dd 33 (v) 5 200 0 50 100 150 rising propagation delay time, tplh ( s) falling propagation delay time, tphl (ns) 0 5 10 rising response time, tr (ns) falling response time, tf (ns) 15 20 0 5 10 15 20 figure 1-9. resp output falling propagation delay time vs. supply voltage 234 supply voltage, v dd 33 (v) 5 234 supply voltage, v dd 33 (v) 5 234 supply voltage, v dd 33 (v) 5 10 0 2 4 6 8 ?1.0e?07 024 13 output voltage, v ol (v) figure 1-7. resn output leakage current vs. output voltage 5 ?5.0e?08 0.0e+00 output leakage current, io leak (a) 5.0e?08 1.0e?07 0.00 0.02 024 13 output voltage, v ol (v) figure 1-6. resn output current vs. output voltage 5 0.04 0.06 output current, i ol (a) 0.08 0.10 v dd 33 = 3.3 v r l , crext = 1 m r l , crext = 1 m r l , crext = 1 m r l , crext = 100 k r l , crext = 100 k r l , crext = 100 k r l , crext = 1 m r l , crext = 100 k v dd 33 = 4.6 v v dd 33 = 2.4 v ta = 25c, v_mr = 0 v ta = 25c, v_mr = v dd 33 v v dd 33 = 2.4 v, v dd 33 = 3.3 v, v dd 33 = 4.6 v
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 18 of 29 aug 03, 2012 figure 1-14. resn output rising response time vs. supply voltage figure 1-15. resn output falling response time vs. supply voltage 234 supply voltage, v dd 33 (v) 5 0 figure 1-16. swg output rising propagation delay time vs. supply voltage figure 1-17. swg output falling propagation delay time vs. supply voltage 50 100 150 200 234 supply voltage, v dd 33 (v) 5 234 supply voltage, v dd 33 (v) 5 234 supply voltage, v dd 33 (v) 5 50 0 10 20 30 40 50 0 10 20 30 40 falling propagation delay time, tphl (ns) 10 0 2 4 6 8 2345 2345 0 50 100 150 200 rising response time, tr (ns) falling response time, tf (ns) supply voltage, v dd 33 (v) 10 0 2 4 6 8 rising propagation delay time, tplh ( s) rising propagation delay time, tphl ( s) falling propagation delay time, tplh ( s) supply voltage, v dd 33 (v) figure 1-12. resn output rising propagation delay time vs. supply voltage figure 1-13. resn output falling propagation delay time vs. supply voltage r l , crext = 1 m r l , crext = 100 k r l , crext = 1 m r l , crext = 100 k c l = 2200 pf , crext = 1 m c l = 2200 pf , crext = 100 k c l = 2200 pf , crext = 1 m c l = 2200 pf , crext = 100 k r l , crext = 1 m r l , crext = 100 k r l , crext = 1 m r l , crext = 100 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 19 of 29 aug 03, 2012 234 supply voltage, v dd 33 (v) 5 falling response time, tr ( s) figure 1-18. swg output rising response time vs. supply voltage figure 1-19. swg output falling response time vs. supply voltage 234 supply voltage, v dd 33 (v) 5 50 0 10 20 30 40 rising response time, tf ( s) 2345 delay time, tdly (ms) 200 0 50 100 150 10 0 2 4 6 8 supply voltage, v dd 33 (v) figure 1-20. reset output delay time vs. supply voltage c l = 2200 pf , crext = 1 m c l = 2200 pf , crext = 100 k c l = 2200 pf , crext = 0.1 f, 1 m c l = 2200 pf , crext = 0.1 f, 100 k c l = 2200 pf , crext = 1 m c l = 2200 pf , crext = 100 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 20 of 29 aug 03, 2012 1.0e?08 1.0e?07 1234 supply voltage, v dd 18 (v) figure 2-1. supply current vs. supply voltage figure 2-2. swg output current vs. output voltage 5 1234 supply voltage, v dd 18 (v) 5 output voltage, v ol (v) 0.010 0.000 0.002 0.004 0.006 0.008 1.0e?06 1.0e?05 supply current, i dd 18 (a) 1.0e?04 1.0e?03 0 figure 2-4. reset output delay time vs. supply voltage 50 100 delay time, tdly (ms) 150 200 ?0.05 ?0.04 024 13 differential output voltage from supply voltage, v oh (v) figure 2-3. swg output current vs. output voltage 5 024 135 ?0.03 ?0.02 output current, i oh (a) output current, i ol (a) ?0.01 0.00 v dd 18 = 1.6 v v dd 18 = 1.8 v v dd 18 = 1.8 v v dd 18 = 4.6 v v dd 18 = 4.6 v ta = 25c, v_mr = v dd 33 v ta = 25c, v_mr = 0 v c l = 2200 pf , crext = 0.1 f, 1 m c l = 2200 pf , crext = 0.1 f, 100 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 21 of 29 aug 03, 2012 figure 3-3. detection voltage vs. ambient temperature 2.90 2.60 2.65 2.70 2.80 2.85 2.75 detection voltage, v th 33 (v) detection voltage hysteresis ratio (%) 0 figure 3-5. detection voltage vs. ambient temperature 0.3 0.6 manual reset threshold voltage, v th mr (v) 1.2 1.8 0.9 1.5 0 1 2 3 4 detection voltage, v th 18h, v th 18l (v) figure 3-4. detection voltage hysteresis vs. ambient temperature 10 0 2 4 6 8 figure 3-6. manual reset threshold voltage vs. ambient temperature 0 2 ?50 0 25 75 ?25 50 ambient temperature, ta (c) figure 3-1. supply current vs. ambient temperature figure 3-2. supply current vs. ambient temperature 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 4 6 supply current, i dd 33 (a) 8 10 0 2 4 6 supply current, i dd 18 (a) 8 10 v ih _rst v il _rst v ih _swg v il _swg v hys v th 33
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 22 of 29 aug 03, 2012 figure 3-7. internal pulled-up resistor vs. ambient temperature figure 3-8. resp output leakage current vs. ambient temperature figure 3-11. resn output leakage current vs. ambient temperature figure 3-9. resp output current vs. ambient temperature figure 3-10. resn output current vs. ambient temperature 0.00 0.02 0.01 0.03 output current, i ol (a) 0.04 0.05 ?1.0e?08 ?5.0e?09 0.0e+00 output leakage current, io leak (a) 5.0e?09 1.0e?08 ?1.0e?08 ?5.0e?09 0.0e+00 5.0e?09 1.0e?08 ?0.020 ?0.015 ?0.010 output current, i oh (a) ?0.005 0.000 output leakage current, io leak (a) ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 0 1 2 4 3 5 resistance value, rmr (m ) v dd 33 = 3.3 v, v dd 18 = 1.8 v, vo = 0 v v dd 33 = 3.3 v, v dd 18 = 1.8 v, v ol = 0.5 v v dd 33 = 3.3 v, v dd 18 = 1.8 v, v ol = 3.3 v v dd 33 = 3.3 v, v dd 18 = 1.8 v, v oh = 2.8 v
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 23 of 29 aug 03, 2012 ?50 0 25 75 ?25 50 ambient temperature, ta (c) figure 3-12. swg output current vs. ambient temperature figure 3-13. swg output current vs. ambient temperature 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?0.010 ?0.008 ?0.006 ?0.004 output current, i oh (a) output current, i ol (a) ?0.002 0.000 figure 3-16. resp output rising response time vs. ambient temperature figure 3-17. resp output falling response time vs. ambient temperature 20 0 5 10 15 20 0 5 10 15 falling propagation delay time, tphl (ns) 10 0 2 4 6 8 0 50 100 150 200 rising response time, tr (ns) falling response time, tf (ns) rising propagation delay time, tplh ( s) figure 3-14. resp output rising propagation delay time vs. ambient temperature figure 3-15. resp output falling propagation delay time vs. ambient temperature 0.0e+00 2.0e?04 4.0e?04 6.0e?04 8.0e?04 1.0e?03 v dd 33 = 3.3 v, v dd 18 = 1.8 v, v ol = 0.5 v v dd 33 = 3.3 v, v dd 18 = 1.8 v, v ol = 1.3 v
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 24 of 29 aug 03, 2012 figure 3-20. resn output rising response time vs. ambient temperature figure 3-21. resn output falling response time vs. ambient temperature 0 50 100 150 200 50 0 10 20 30 40 50 0 10 20 30 40 falling propagation delay time, tphl (ns) 10 0 2 4 6 8 0 50 100 150 200 rising response time, tr (ns) falling response time, tf (ns) 10 0 2 4 6 8 rising propagation delay time, tplh ( s) falling propagation delay time, tphl ( s) rising propagation delay time, tplh ( s) figure 3-18. resn output rising propagation delay time vs. ambient temperature figure 3-19. resn output falling propagation delay time vs. ambient temperature figure 3-22. swg output falling propagation delay time vs. ambient temperature figure 3-23. swg output rising propagation delay time vs. ambient temperature ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 25 of 29 aug 03, 2012 figure 3-26. reset output delay time vs. ambient temperature 0.1 figure 4-1. reset output delay time vs. external resistor figure 4-2. reset output delay time vs. external capacitance 1 10 100 1000 figure 3-25. swg output rising response time vs. ambient temperature figure 3-24. swg output falling response time vs. ambient temperature ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 ?50 0 25 75 ?25 50 ambient temperature, ta (c) 100 1 10 100 1000 0.001 0.010 0.100 external capacitance, cext ( f) external resistor, rext (k ) 1.000 rising response time, tr ( s) 50 0 10 20 30 40 falling response time, tf ( s) delay time, tdly (ms) delay time, tdly (ms) 0.1 1 10 100 1000 delay time, tdly (ms) 200 0 50 100 150 10 0 2 4 6 8 10 m 0.33 f 0.1 f 0.033 f 1 m 100 k
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 26 of 29 aug 03, 2012 package dimensions rna50c27aus 2.4 0.80.7 1.8 2.2 0.6 a l e e c 1 b 1 d e a 2 b p c x y h e z l 1 2.0 (0.4) 3.1 0.08 0.13 0.23 0.3 0 0.1 2.3 reference symbol dimension in millimeters min nom max 2.2 a 1 0.15 0.22 3.4 2.8 (0.5) 0.11 0.20 p f 1 e 4 85 b h e 0.17 () d 1.5 0.2 1 1 terminal cross section p b c c b detail f 1 2 1 l a a p-vssop8-2.3x2-0.50 0.010g mass[typ.] ttp-8db/ttp-8dbv pvsp0008ka-a renesas code jeita package code previous code unit: mm these numbers on the diagram are reference values. please adjust size, space, and other area of footprint as needed. note: ssop-8 footprint example 0.5 0.3 0.5 0.5 0.2 0.1 0.4 2.3 3.1
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 27 of 29 aug 03, 2012 rna50c27amm mass[typ.] ? plsp0008jc-a 0.02 g p-lsop8-2.8 x 2.95 - 0.65 renesas code jeita package code previous code unit: mm package name mmpak-8 0.1 m 0.1 2.95 0.2 1.95 1.1 0.1 4.0 0.3 2.8 0.1 0.6 0.3 0.13 0 to 0.1 0.65 +0.12 -0.03 0.2 +0.1 -0.05 unit: mm mmpak-8 footprint example 0.35 0.65 3.2 0.75 0.75 4.7
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 28 of 29 aug 03, 2012 taping and reel specifications ssop-8 13 0.5 178 2 13.0 9.0 2.0 0.5 4 0.5 reel type: c 120 unit: mm 1.05 4 0.3 1.5 2.25 8 3.5 1.75 42 3.4 1.0 maximum storage no.: 3000 pcs./reel mmpak-8 13 0.5 178 2 17.0 13.0 2.0 0.5 4 0.5 reel type: c 120 unit: mm 1.05 4 0.3 1.55 3.35 12.0 5.5 1.75 42 4.5 1.0 maximum storage no.: 3000 pcs./reel
rna50c27a preliminary r03ds0064ej0100 rev.1.00 page 29 of 29 aug 03, 2012 mark indication (1) (2) (3) n 0 1 r 02 (1) (2) (3) rna50c27aus rna50c27amm (1) year code the last digit of year (2) month code starting in january "a","b ","c","d","e","f","g", "h","j","k","l","m" (3) week code view week of month, 1 week ? "1"
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